Substrate Noise Coupling in RFICs

Coupling takes place due to the capacitive and resistive nature of the substrate-devices interface. ... Certain types of circuits have traditionally been built on separate substrates in order to minimize noise coupling between them.

Substrate Noise Coupling in RFICs

The book reports modeling and simulation techniques for substrate noise coupling effects in RFICs and introduces isolation structures and design guides to mitigate such effects with the ultimate goal of enhancing the yield of RF and mixed signal SoCs. The book further reports silicon measurements, and new test and noise isolation structures. To the authors’ knowledge, this is the first title devoted to the topic of substrate noise coupling in RFICs as part of a large SoC.

Substrate Noise

The impact of several physical parameters and isolation techniques on substrate noise is discussed by means of experiments and simulations. These include separation between the injector and the sensor nodes, the use of guard rings and ...

Substrate Noise

In the past decade, substrate noise has had a constant and significant impact on the design of analog and mixed-signal integrated circuits. Only recently, with advances in chip miniaturization and innovative circuit design, has substrate noise begun to plague fully digital circuits as well. To combat the effects of substrate noise, heavily over-designed structures are generally adopted, thus seriously limiting the advantages of innovative technologies. Substrate Noise: Analysis and Optimization for IC Design addresses the main problems posed by substrate noise from both an IC and a CAD designer perspective. The effects of substrate noise on performance in digital, analog, and mixed-signal circuits are presented, along with the mechanisms underlying noise generation, injection, and transport. Popular solutions to the substrate noise problem and the trade-offs often debated by designers are extensively discussed. Non-traditional approaches as well as semi-automated techniques to combat substrate noise are also addressed. Substrate Noise: Analysis and Optimization for IC Design will be of interest to researchers and professionals interested in signal integrity, as well as to mixed signal and RF designers.

Substrate Noise Coupling in Analog RF Circuits

Substrate. Noise. Propagation. 2.1 INTRODUCTION Current deep submicron technologies use a lightly doped substrate (20 Ωcm). This type of substrate has better substrate noise isolation properties than the epi- type substrate [1–3] (0.1 ...

Substrate Noise Coupling in Analog RF Circuits

This book presents case studies to illustrate that careful modeling of the assembly characteristics and layout details is required to bring simulations and measurements into agreement. Engineers learn how to use a proper combination of isolation structures and circuit techniques to make analog/RF circuits more immune to substrate noise. Topics include substrate noise propagation, passive isolation structures, noise couple in active devices, measuring the coupling mechanisms in analog/RF circuits, prediction of the impact of substrate noise on analog/RF circuits, and noise coupling in analog/RF systems.

Substrate Noise Coupling in Mixed Signal ASICs

Since in most cases ringing of the power supply is the major source of substrate noise generation, techniques targeting at shaping the supply current and its transfer function to the substrate can reduce substrate noise generation ...

Substrate Noise Coupling in Mixed Signal ASICs

This book is the first in a series of three dedicated to advanced topics in Mixed-Signal IC design methodologies. It is one of the results achieved by the Mixed-Signal Design Cluster, an initiative launched in 1998 as part of the TARDIS project, funded by the European Commission within the ESPRIT-IV Framework. This initiative aims to promote the development of new design and test methodologies for Mixed-Signal ICs, and to accelerate their adoption by industrial users. As Microelectronics evolves, Mixed-Signal techniques are gaining a significant importance due to the wide spread of applications where an analog front-end is needed to drive a complex digital-processing subsystem. In this sense, Analog and Mixed-Signal circuits are recognized as a bottleneck for the market acceptance of Systems-On-Chip, because of the inherent difficulties involved in the design and test of these circuits. Specially, problems arising from the use of a common substrate for analog and digital components are a main limiting factor. The Mixed-Signal Cluster has been formed by a group of 11 Research and Development projects, plus a specific action to promote the dissemination of design methodologies, techniques, and supporting tools developed within the Cluster projects. The whole action, ending in July 2002, has been assigned an overall budget of more than 8 million EURO.

Power Thermal Noise and Signal Integrity Issues on Substrate Interconnects Entanglement

O. Valorge, C. Andrei, B. Vrignon, F. Calmon, C. Gontrand, J. Verdier, and P. Dautriche, Using ICEM models for substrate noise characterization in mixed signal IC's. Zurich International Symposium on Electromagnetic Compatibility, pp.

Power  Thermal  Noise  and Signal Integrity Issues on Substrate Interconnects Entanglement

As demand for on-chip functionalities and requirements for low power operation continue to increase as a result of the emergence in mobile, wearable and internet-of-things (IoT) products, 3D/2.5D have been identified as an inevitable path moving forward. As circuits become more and more complex, especially three-dimensional ones, new insights have to be developed in many domains, including electrical, thermal, noise, interconnects, and parasites. It is the entanglement of such domains that begins the very key challenge as we enter in 3D nano-electronics. This book aims to develop this new paradigm, going to a synthesis beginning between many technical aspects.

Substrate Noise

Popular solutions to the substrate noise problem and the trade-offs often debated by designers are extensively discussed. Non-traditional approaches as well as semi-automated techniques to combat substrate noise are also addressed.

Substrate Noise


Characterization of Substrate Noise Coupling Its Impacts and Remedies in RF and Mixed signal ICs

Several effects of substrate coupling on circuit performance will be identified and remedies will be given based on the design guide. Three case studies are designed to analyze the substrate coupling problem in RFICs.

Characterization of Substrate Noise Coupling  Its Impacts and Remedies in RF and Mixed signal ICs

Abstract: Substrate noise coupling in integrated circuits is the process by which interference signals generated by high speed digital blocks cause parasitic currents to flow in the silicon substrate and couple devices in various parts of the circuits on this common substrate. In RFIC the switching noise couples to the sensitive analog circuits through the substrate causing degradation in performance and yield hit. Overcoming substrate coupling is a key issue in successful "system on chip" integration. In this thesis a substrate aware design flow is built, calibrated to silicon and used as part of the design flow to uncover substrate coupling problems in RFICs in the design phase. The flow is used to develop the first comprehensive RF substrate noise isolation design guide to be used by RF designers during the design phase. This will allow designers to optimize the design to maximize noise isolation and protect sensitive blocks from being degraded by substrate noise coupling. Several effects of substrate coupling on circuit performance will be identified and remedies will be given based on the design guide. Three case studies are designed to analyze the substrate coupling problem in RFICs. The case studies are designed to attack the problem from the device, circuit and system levels. On the device level a special emphasis is given to designing on chip inductors as an important device in RFIC. An accurate model is developed for a broadband fit of the inductor scattering parameters. This model is shown to be scalable and is proven to be accurate across various frequency bands and geometries. A special emphasis is put on the design for manufacturing effects that affect the design robustness. A circuit level case study is developed and results are compared to simulations and measurements to highlight the need for such a flow before tapping out to ensure a yielding part. The system level problem studied is a GSM receiver where the research results are directly applied to it as a demonstration vehicle to debug and resolve a system level substrate noise coupling problem that otherwise caused a product to be on the edge of malfunction.

The Electronic Design Automation Handbook

GND noise source NMOS substrate contact 1 transistor disturbed VDD substrate contact 2 p+ n+ capacitivenoise coupling 3 p substrate (Epi) R 22 R1 R21 face currents in the low resistive channel stoppers [21.22].

The Electronic Design Automation Handbook

When I attended college we studied vacuum tubes in our junior year. At that time an average radio had ?ve vacuum tubes and better ones even seven. Then transistors appeared in 1960s. A good radio was judged to be one with more thententransistors. Latergoodradioshad15–20transistors and after that everyone stopped counting transistors. Today modern processors runing personal computers have over 10milliontransistorsandmoremillionswillbeaddedevery year. The difference between 20 and 20M is in complexity, methodology and business models. Designs with 20 tr- sistors are easily generated by design engineers without any tools, whilst designs with 20M transistors can not be done by humans in reasonable time without the help of Prof. Dr. Gajski demonstrates the Y-chart automation. This difference in complexity introduced a paradigm shift which required sophisticated methods and tools, and introduced design automation into design practice. By the decomposition of the design process into many tasks and abstraction levels the methodology of designing chips or systems has also evolved. Similarly, the business model has changed from vertical integration, in which one company did all the tasks from product speci?cation to manufacturing, to globally distributed, client server production in which most of the design and manufacturing tasks are outsourced.

Towards a Modeling Synthesis of Two or Three Dimensional Circuits Through Substrate Coupling and Interconnections Noises and Parasites

PART I: GROUND OR SUPPLY NOISE AND SUBSTRATE COUPLING 1.1. GROUND AND SUBSTRATE NOISE MECHANISMS In our point of view, substrate perturbations could be the core subject dealing with very complex circuits. We will describe the different ...

Towards a Modeling Synthesis of Two or Three Dimensional Circuits Through Substrate Coupling and Interconnections  Noises and Parasites

The number of transistors in integrated circuits doubles every two years, as stipulated by Moore’s law, and this has been the driving force for the huge development of the microelectronics industry in the past 50 years – currently advanced to the nanometric scale. This e-book is dedicated to electronic noises and parasites, accounting for issues involving substrate coupling and interconnections, in the perspective of the 3D integration: a second track for enhancing integration, also compatible with Moore’s law. This reference explains the modeling of 3D circuits without delving into the latest advances, but highlights crucial problems, for instance electro-thermo-mechanical problems, which could be addressed through 3D modeling. The book also explains electromagnetic interferences , at different modeling levels (device and circuit) oriented towards 3D integration technologies. It also covers substrate noise, such as disturbances of digital blocks, power bounces, phase noise in oscillators, both at the device level, such as carriers or field fluctuations, and circuit levels. The entanglement between interconnect and substrate is also discussed. This e-book serves as a reference for advanced graduates or researchers in the field of micro and nano electronics interested in topics relevant to electromagnetic interference or the ‘noise’ domain, at device or circuit and system levels

Analog Circuit Design

This highly doped bulk-substrate acts as an equipotential node and distributes the injected noise over the whole chip [5]. This chip wide, common-mode substrate noise couples in a different way to NMOS and PMOS transistors, ...

Analog Circuit Design

This book contains the extended and revised editions of all the talks of the ninth AACD Workshop held in Hotel Bachmair, April 11 - 13 2000 in Rottach-Egem, Germany. The local organization was managed by Rudolf Koch of Infineon Technologies AG, Munich, Germany. The program consisted of six tutorials per day during three days. Experts in the field presented these tutorials and state of the art information is communicated. The audience at the end of the workshop selects program topics for the following workshop. The program committee, consisting of Johan Huijsing of Delft University of Technology, Willy Sansen of Katholieke Universiteit Leuven and Rudy van de Plassche of Broadcom Netherlands BV Bunnik elaborates the selected topics into a three-day program and selects experts in the field for presentation. Each AACD Workshop has given rise to publication of a book by Kluwer entitled "Analog Circuit Design". A series of nine books in a row provides valuable information and good overviews of all analog circuit techniques concerning design, CAD, simulation and device modeling. These books can be seen as a reference to those people involved in analog and mixed signal design. The aim of the workshop is to brainstorm on new and valuable design ideas in the area of analog circuit design. It is the hope of the program committee that this ninth book continues the tradition of emerging contributions to the design of analog and mixed signal systems in Europe and the rest of the world.

VLSI Systems on a Chip

Specific guidelines have also becm drafted for more aggressive, substrate-aware design practices. Accurately characterizing substrate noise is problematic for various reasons. The noise results from superposition of a large number of ...

VLSI  Systems on a Chip

For over three decades now, silicon capacity has steadily been doubling every year and a half with equally staggering improvements continuously being observed in operating speeds. This increase in capacity has allowed for more complex systems to be built on a single silicon chip. Coupled with this functionality increase, speed improvements have fueled tremendous advancements in computing and have enabled new multi-media applications. Such trends, aimed at integrating higher levels of circuit functionality are tightly related to an emphasis on compactness in consumer electronic products and a widespread growth and interest in wireless communications and products. These trends are expected to persist for some time as technology and design methodologies continue to evolve and the era of Systems on a Chip has definitely come of age. While technology improvements and spiraling silicon capacity allow designers to pack more functions onto a single piece of silicon, they also highlight a pressing challenge for system designers to keep up with such amazing complexity. To handle higher operating speeds and the constraints of portability and connectivity, new circuit techniques have appeared. Intensive research and progress in EDA tools, design methodologies and techniques is required to empower designers with the ability to make efficient use of the potential offered by this increasing silicon capacity and complexity and to enable them to design, test, verify and build such systems.

International Conference on Wireless Intelligent and Distributed Environment for Communication

The probability density function of the substrate noise using the discussed algorithm is estimated. The priori update values are set, and post priori update values for the each parameter are evaluated; on the basis of these updates, ...

International Conference on Wireless  Intelligent  and Distributed Environment for Communication

This book presents the proceedings of the International Conference on Wireless Intelligent and Distributed Environment for Communication (WIDECOM 2018), organized by SRM University, NCR Campus, New Delhi, India, February 16-18, 2018. The conference focuses on challenges with respect to the dependability of integrated applications and intelligence-driven security threats against the platforms supporting these applications. The WIDECOM 2018 proceedings features papers addressing issues related to the new dependability paradigms, design, control, and management of next generation networks, performance of dependable network computing and mobile systems, protocols that deal with network computing, mobile/ubiquitous systems, cloud systems, and Internet of Things (IoT) systems. The proceeding is a valuable reference for researchers, instructors, students, scientists, engineers, managers, and industry practitioners, in industry, in the aforementioned areas. The book’s structure and content is organized in such a manner that makes it useful at a variety of learning levels. Presents the proceedings of the International Conference on Wireless Intelligent and Distributed Environment for Communication (WIDECOM 2018), organized by SRM University, NCR Campus, New Delhi, India, February 16-18, 2018; Includes an array of topics related to new dependability paradigms, design, control, and management of next generation networks, performance of dependable network computing and mobile systems, protocols that deal with network computing, mobile/ubiquitous systems, cloud systems, and Internet of Things (IoT) systems; Addresses issues related to the design and performance of dependable network computing and systems and to the security of these systems.

Silencer

This thesis presents Silencer!, a fully automated, schematic-driven tool for substrate noise coupling simulation and analysis.

Silencer

This thesis presents Silencer!, a fully automated, schematic-driven tool for substrate noise coupling simulation and analysis. It has been integrated in the CADENCE DFII environment and seamlessly enables substrate coupling analysis in a standard mixed-signal design flow. Silencer! aids IC designers in the analysis of substrate noise coupling at different levels of hierarchy - from a level where only an approximate layout of the transistors is known to a level that incorporates various parasitic elements. It can be used for layout optimization to reduce substrate cross-talk noise between circuitry that injects noise into the substrate and other circuitry that is sensitive to it. Examples in a TSMC 0.35[mu]m heavily doped process have been simulated and the results are in good agreement with measured fabricated chips.

Introduction to Avionics Systems

The mechanism of di / dt noise is often the dominant cause of substrate noise , especially if interconnect inductance and substrate biasing schemes are poorly designed . The resulting substrate voltage waveform of the dv / dt noise are ...

Introduction to Avionics Systems

Evaluation copies are available. Please contact [email protected] Provide the course number, number of students and present textbook used.Introduction to Avionics Systems, Second Edition explains the basic principles and underlying theory of modern avionic systems and how they are implemented with current technology for both civil and military aircraft in a clear and easy to read manner.All systems are explained so that their design and performance can be understood and analysed. Worked examples are included to illustrate the application of the theory and principles covered. The latest developments and directions of research for future systems are included.This new second edition has approximately 25% new material and takes into account the technology developments which have taken place since the first edition was published in January 1996. The book is well illustrated with line drawings and photos, with some in colour where appropriate.Readership: Graduates (or equivalent) from a range of disciplines entering the avionics and aerospace industries.Engineers at all levels engaged in the design and development of avionic systems and equipment in the avionic and aerospace industries.Students and post graduate students taking avionics and aeronautical engineering courses.Staff in the armed services and civil airlines engaged in the support or operation of aircraft who wish to acquire a deeper understanding of the design and implementation of avionic systems and equipment.

Noise Coupling in System on Chip

Noise Coupling is the root-cause of the majority of Systems on Chip (SoC) product fails. The book discusses a breakthrough substrate coupling analysis flow and modelling toolset, addressing the needs of the design community.

Noise Coupling in System on Chip

Noise Coupling is the root-cause of the majority of Systems on Chip (SoC) product fails. The book discusses a breakthrough substrate coupling analysis flow and modelling toolset, addressing the needs of the design community. The flow provides capability to analyze noise components, propagating through the substrate, the parasitic interconnects and the package. Using this book, the reader can analyze and avoid complex noise coupling that degrades RF and mixed signal design performance, while reducing the need for conservative design practices. With chapters written by leading international experts in the field, novel methodologies are provided to identify noise coupling in silicon. It additionally features case studies that can be found in any modern CMOS SoC product for mobile communications, automotive applications and readout front ends.

Microwave and Millimeter Wave Circuits and Systems

For the previously reported work on the effects of substrate noise on analogue/RF integrated circuits (ICs), almost all of them are focusing on narrowband applications [8– 11].Ithas notbeenfullyinvestigated ifsubstratenoiseisasevere ...

Microwave and Millimeter Wave Circuits and Systems

Microwave and Millimeter Wave Circuits and Systems: EmergingDesign, Technologies and Applications provides a wide spectrumof current trends in the design of microwave and millimetercircuits and systems. In addition, the book identifies thestate-of-the art challenges in microwave and millimeter wavecircuits systems design such as behavioral modeling of circuitcomponents, software radio and digitally enhanced front-ends, newand promising technologies such as substrate-integrated-waveguide(SIW) and wearable electronic systems, and emerging applicationssuch as tracking of moving targets using ultra-wideband radar, andnew generation satellite navigation systems. Each chapter treats aselected problem and challenge within the field of Microwave andMillimeter wave circuits, and contains case studies and exampleswhere appropriate. Key Features: Discusses modeling and design strategies for new appealingapplications in the domain of microwave and millimeter wavecircuits and systems Written by experts active in the Microwave and Millimeter Wavefrequency range (industry and academia) Addresses modeling/design/applications both from the circuit asfrom the system perspective Covers the latest innovations in the respective fields Each chapter treats a selected problem and challenge within thefield of Microwave and Millimeter wave circuits, and contains casestudies and examples where appropriate This book serves as an excellent reference for engineers,researchers, research project managers and engineers working inR&D, professors, and post-graduates studying related courses.It will also be of interest to professionals working in productdevelopment and PhD students.

Power Integrity for Nanoscale Integrated Systems

Another issue is substrate noise. Figure 2.2 illustrates three mechanisms that cause substrate noise in an inverter: (1) impact ionization, (2) source/drain coupling, and (3) supply coupling. Impact ionization current is the hole ...

Power Integrity for Nanoscale Integrated Systems

Proven methods for noise-tolerant nanoscale integrated circuit design This leading-edge guide discusses the impact of power integrity from a design perspective, emphasizing phenomena and problems induced by power integrity degradation and the latest design trends, including low-power design. Power Integrity for Nanoscale Integrated Systems describes how these problems can be forecast early in the design process and the countermeasures that can be used to address them, such as the inclusion of inductance and accurate modeling for PI analysis, as well as robust circuit design. Detailed examples and a case study on the IBM POWER7+ processor illustrate real-world applications of the techniques presented in this practical resource. Coverage includes: Significance of power integrity for integrated circuits Supply and substrate noise impact on circuits Clock generation and distribution with power integrity Signal and power integrity design for I/O circuits Power integrity degradation and modeling Lumped, distributed, and 3D modeling for power integrity Chip temperature and PI impact Low-power techniques and PI impact Power integrity case study using the IBM POWER7+ processor chip Carbon nanotube interconnects for power delivery

Design of High Performance CMOS Voltage Controlled Oscillators

Despite the above benefits , it is a commonly held belief that single - ended circuits suffer from power supply and substrate noise injection when the oscillator is implemented on the same silicon substrate with digital circuits .

Design of High Performance CMOS Voltage Controlled Oscillators

Voltage-controlled oscillators (VCOs) with low phase noise are the most critical building block in high performance phase-locked loops (PLL). Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion for the bias circuits should be minimized. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Our phase noise analysis is validated via simulation and measurement results. The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present. Design of High-Performance CMOS Voltage-Controlled Oscillators noise, analyzes the impact of the supply and substrate noise on the oscillator phase noise, and suggests techniques for reducing the jitter due to the supply and substrate noise. The primary audience for Design of High-Performance CMOS Voltage-Controlled Oscillators is research workers and design engineers who concentrate on high performance communication circuits. This work will also be of interest to analog circuit designers.

Device Modeling for Analog and RF CMOS Circuit Design

... for the induced gate noise and its correlation to the drain noise, αg is the ratio of the noise PSD of the gate resistance to the input referred channel noise, and αsub is the ratio of the output referred substrate resistance noise ...

Device Modeling for Analog and RF CMOS Circuit Design

Bridges the gap between device modelling and analog circuit design. Includes dedicated software enabling actual circuit design. Covers the three significant models: BSIM3, Model 9 &, and EKV. Presents practical guidance on device development and circuit implementation. The authors offer a combination of extensive academic and industrial experience.

Mixed Signal Methodology Guide

In a mixed-signal chip, analog and digital circuits reside on the same silicon substrate. Fast, simultaneously switching digital circuits inject noise into the substrate through the coupling between the substrate and the power/ground ...

Mixed Signal Methodology Guide